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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:18:12 11/16/2010 
-- Design Name: 
-- Module Name:    Res_Buffer - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.CONSTANTS.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Res_Buffer is
    Port ( clk : in  std_logic;
           reset : in  std_logic;
           data_in : in  std_logic_vector (DATA_SIZE-1 downto 0);
           store : in  std_logic;
           addr : in  std_logic_vector(ADDR_SIZE_RESBUFFER-1 downto 0);
           data_out : out  std_logic_vector (DATA_SIZE-1 downto 0));
end Res_Buffer;

architecture Behavioral of Res_Buffer is

component One_hot_count4 is
    Port ( reset : in  STD_LOGIC;
           advance : in  STD_LOGIC;
			  clk : in STD_LOGIC;
           count_out : out  STD_LOGIC_VECTOR (ADDR_SIZE_RESBUFFER-1 downto 0) );
end component;

component REG32 is
	port (
		data_in		:	in std_logic_vector(DATA_SIZE-1 downto 0);
		data_out	:	out std_logic_vector(DATA_SIZE-1 downto 0);
		we			:	in std_logic;
		clk			:	in std_logic;
		reset		:	in std_logic
	);
end component;

signal outcount : std_logic_vector (ADDR_SIZE_RESBUFFER-1 downto 0);
signal reg0out, reg1out, reg2out, reg3out : std_logic_vector(DATA_SIZE-1 downto 0);
signal reg0en, reg1en, reg2en, reg3en : std_logic;
begin

-- purpose : Destination register selection
-- type    : sequential
reg0en <= store and outcount(0);
reg1en <= store and outcount(1);
reg2en <= store and outcount(2);
reg3en <= store and outcount(3);

-- purpose : Interna pointer
-- type    : structural
counter : One_hot_count4
	port map(reset, store, clk, outcount);

-- purpose : 4 Internal registers
-- type    : behavioral
reg0 : REG32
   port map(data_in, reg0out, reg0en, clk, reset);

reg1 : REG32
   port map(data_in, reg1out, reg1en, clk, reset);

reg2 : REG32
   port map(data_in, reg2out, reg2en, clk, reset);

reg3 : REG32
   port map(data_in, reg3out, reg3en, clk, reset);

   
-- purpose : output selection
-- type    : behavioral
buffer_exit : process(addr, reg0out, reg1out, reg2out, reg3out)
begin
case addr is 
	when "0001" =>
		data_out <= reg0out;
	when "0010" =>
		data_out <= reg1out;
	when "0100" =>
		data_out <= reg2out;
	when "1000" => 
		data_out <= reg3out;
	when others =>
		data_out <= (others => '0');
end case;
end process;
	
end Behavioral;


